1. Field of the Invention
The present invention relates to a MPEG decoder and more particularly to a memory allocation technique for decoded image data in the MPEG decoder.
2. Background of the Related Art
FIG. 1 shows a construction of an READ/WRITE controller of SDRAM in the MPEG decoder, which includes a display controller 1, a motion compensator 2, a audio/subpicture processing unit 3, a SDRAM 4, and a memory controller 5. The display controller 1, the motion compensator 2, and the audio/subpicture processing unit 3 are all linked to the memory controller 5 by an address and data bus (iaddr, idbus) and a control bus. The memory controller 5 is also linked to the SDRAM 4 by control signals, memory address (maddr) and memory data bus (mdbus).
The recovery of the image data from the input compressed data, the motion compensation, the audio/video signal processing, and display processing are accomplished in the display controller 1, the motion compensator 2, and the audio/subpicture processing unit 3 by accessing the SDRAM 4 through the memory controller 5. The MPEG image data is stored in the external memory SDRAM 4 and is read repeatedly by the display controller 1 and the motion compensator 2. The MPEG image data for a picture is generally divided into macro blocks (MB0 . . . MBn*mxe2x88x921) as shown in FIG. 2 having a luminescence of 16*16 and color data.
A timing diagram of the READ cycle for the SDRAM 4 is shown in FIG. 3, wherein a clk represents a clock signal, a csb represents a chip select signal, a rasb represents a row address strobe signal, a casb represents a column address strobe signal, a maddr represents a memory address signal, and a mdbus represents a memory data signal. Also, a Trcd representing an active to column command requires 3 clks, a Tras representing an active to precharge requires 6 clks, a Trp representing a precharge to active requires 3 clks, a Tapr representing a last data out to active requires 1 clk, a Trc representing a row cycle time requires 9 clks, and a Trrd representing an active to active bank requires 2 clks.
As shown in FIG. 3, in order to read the data stored in the SDRAM 4, the appropriate bank must first be precharged prior to activating the bank and a row. Upon activation of the row, a column address is designated and the data is read after a fixed of column latency (CL). Following the read process, the bank is precharged for the next read cycle.
During the reading process, the data in a different bank may be read continuously even if the data is in a different row, as shown in FIG. 4. However, the data in a different row of the same bank may be read only after an internal precharging and an activation of the new row and bank, as shown in FIG. 5. The data in a different row of the same bank cannot be read continuously. A period of Tpenalty, usually 6 cycles, is required to read such data. FIG. 6 shows a memory map obtained by an allocation method in the related art. Such allocation method results in the case as shown in FIG. 5 and is generally used as a method for storing a decoded image data.
The allocation method illustrated in FIG. 6 is a technique for continuously storing pixels in the units of scan lines depending upon the display system used. The same hatching indicates one scanning line. In this case, an interlaced scanning is performed to map the top and bottom fields and the motion vectors are stored at random. When motion vectors are designated as shown in FIG. 6, data should be read in the order of 1, 2, 3, 4 for the purpose of field motion compensation.
However, the data are stored in four different rows of the same bank. As a result, the data cannot be read continuously, but must be cut-off or interrupted three times with the Tpenalty period. Because the time required for reading data stored according to this allocation method greatly depends on the storage location of the data, the maximum value of the bandwidth is significantly increased as the data are stored randomly.
In decoding a Bidirectional (B) frame type of picture, the decoder repeatedly requires the data of an Intra (I) and Predictive (P) frame types of pictures which have been decoded by an MPEG decoder. Because the amount of data required in one reading low, the time to process all the necessary data for transmission takes a large portion of the time available to transfer the data. Thus, a wide bandwidth is required.
Also, the data for motion compensation at the MPEG decoder are situated over several scan lines. Thus, the data for motion compensation cannot be read and transmitted continuously, but requires a delay time. Accordingly, the bandwidth of memory is again increased.
The present invention proposes a memory allocation method and its apparatus for storing a decoded image data as macro block sets. According to the present invention, the decoded image data are grouped in blocks appropriate to the size of the memory. Thereafter, the data blocks are stored in the memory, thereby minimizing the cut-off effect in reading out the data and reducing the memory bandwidth required. Thus, the present allocation method allows a high speed reading of data.
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide a memory allocation method for an efficient reading and writing a decoded image data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a memory allocation method according to the present invention stores/reads the decoded data in block sets in/from a memory by grouping the data blocks into sets of blocks and storing the block sets in the memory in block sets.
In another embodiment of the present invention, a memory allocation apparatus includes a memory storing and outputting the data in the unit of block sets, and a memory controller controlling the storing/reading of data in the block sets in/from the memory. The memory controller also constructs set of blocks by grouping a plurality of the data into one block set, the number of data to be grouped being the maximum number nearest to the allowable range of memory size. The memory controller includes a counter determining the number of macro blocks and a direction determination unit determining the direction in construction of the block sets according to the number of blocks of the display data in the vertical or horizontal direction. The block set is constructed by grouping the display data in the block unit vertically or horizontally.